Column redundancy allows a memory array to replace a bad column with a redundant column. This redundancy can be performed using the granularity of sense amplifier (SA) shifting or I/O shifting. In both types of memory redundancy, the memory array includes both even and odd columns. To read an even word from the memory, the sense amplifiers in the even columns are enabled. Similarly, just the sense amplifiers in the odd columns are enabled to read an odd word from the memory. With regard to these column types, sense amplifier shifting is denser since just a sense amplifier bitslice is used to replace a defective column, regardless of whether the defective column is even or odd. In contrast, memory redundancy through I/O shifting requires a redundant even column and a redundant odd column. I/O shifting is thus less dense since it requires more redundant columns than sense amplifier shifting memory redundancy schemes.
Although sense amplifier shifting is advantageously denser, the implementation of a generic redundant column that can be instantiated as either a replacement for a defective even column or for a defective odd column has required complicated control logic. For example, a memory 100 with sense-amplifier shifting is shown in FIG. 1. Two independent memory arrays or banks are included in memory 100: a bank 1 array and a bank 0 array. Each memory bank has its own set of sense amplifiers 101 for sensing the memory bank's bit lines. In particular, each sense amplifier 101 senses from four corresponding bit lines 102 for its corresponding memory bank. There is thus a 4:1 bit-line multiplexing with regard to each sense amplifier 101 for a given memory bank. After sensing a memory cell within the corresponding memory bank through the 4:1 bit line multiplexing, each sense amplifier 101 drives the corresponding binary bit decision onto a read line 104. The read lines 104 are shared by memory bank 0 and by memory bank 1. The bit lines 102, memory cells in bank 0 and bank 1 as well as the corresponding sense amplifiers 101 and read line 104 are denoted herein as a “column.” In other words, a column 135 refers to the structure in any given memory bank to drive a sense amplifier's read line 104. That structure would of course include sense amplifier 101 and the associated bit lines 102 and memory cells coupled to those bit lines 102.
For illustration clarity, only a single initial column 135 and a subsequent column 135 are demarcated by dotted lines in memory 100. Each column 135 includes four corresponding bit lines 102 in memory bank 0 and memory bank 1. As known in the memory arts, each sense amplifier 101 is configured to respond to a sense enable signal (not illustrated). If the sense enable signal to a given sense amplifier 101 is asserted, that sense amplifier 101 will drive out a bit decision onto its read line 104.
Memory 100 responds to a read operation by outputting a retrieved word Dout from an output stage 120. Dout is a 32-bit wide retrieved word ranging from a first word bit Dout[1] to a last word bit Dout[32]. Each word Dout can either be an odd (O) word or an even (E) word depending upon whether it was sensed from odd or even columns. In other words, columns 135 are divided into even (E) and odd (O) columns. An even column includes an even sense amplifier for each memory bank. Similarly, an odd column includes an odd sense amplifier for each memory bank. A first even column and a first odd column correspond to Dout[1], depending upon whether the word is odd or even. Similarly, a second even column and a second odd column correspond to Dout[2], and so on such that a 32nd even column and a 32nd odd column correspond to Dout[32]. Given this odd or even value for each word bit, a first stage of 2:1 multiplexers 125 in output stage 120 enables an 8:1 bit line multiplexing with regard to each word bit.
Just like the odd and even column pairs, each multiplexer 125 corresponds to a bit position in the word Dout. For example, a first multiplexer 125 corresponds to Dout[1], a second multiplexer 125 corresponds to Dout[2], and so on. Each multiplexer 125 can select between the even and odd columns for its corresponding word bit with regard to its S1 and S2 inputs. For example, an initial multiplexer 125 receives the read line 104 for the first even column 135 at an S2 input and receives the read line 104 for the first odd column at an S1 input. Each multiplexer 125 may thus be considered to receive an odd input and an even input.
The sense enable signal to sense amplifiers 101 differentiate between even and odd columns and also between banks. The sense enable signal for a given memory bank may thus have a even state that triggers the sensing of the even bits from the even sense amplifiers and have an odd state that triggers the sensing of the odd bits from the odd sense amplifiers. In a default state (no column errors), multiplexers 125 are then controlled to select for their odd or even inputs depending upon whether Dout is an odd or even word.
Because of the sharing of a single read line 104 across both memory banks, a defect in just the memory bank 1 portion or in in just memory bank 0 portion of a given column 135 destroys the usefulness of that even or odd column. Such a defective column is replaced in a sense-amplifier redundancy scheme by a subsequent column for the same odd or even class. To perform this replacement requires a second stage of multiplexers 130 in output stage 120.
There is one multiplexer 130 for each bit in the output word Dout. Thus, a first multiplexer 130 selects for Dout[1], a second multiplexer 130 selects for Dout[2], and so on. Because of the two stages of 2:1 multiplexing, each multiplexer 130 except for a last multiplexer 130 for Dout[32] can ultimately select from the bit decisions from two even and odd column pairs. A bit decision from the even and odd column pair for a given word bit may be said to be the unshifted bit decision for that output bit's multiplexer 130 as received at an S2 input. For example, a bit decision from the first bit even and odd columns would be an unshifted bit decision for the multiplexer 130 for Dout[1]. In addition, each multiplexer 130 from the first multiplexer 130 through a next-to-last multiplexer 130 has an S1 input for receiving a bit decision from the subsequent bit's even and odd column pair. This bit decision may be denoted as the shifted bit decision. For example, the first multiplexer 130 can select for the bit decision from the second bit even and odd column pair at its S1 input. But there is no subsequent column for the thirty-second bit's even and odd column. The S1 input for this final bit's multiplexer 130 receives a redundant read line 145 from a redundant column 140. Redundant column 140 includes a redundant sense amplifier 105 for each memory bank.
For example, suppose an even column is defective but an odd word is being read from memory 100. In such a case, each multiplexer 130 is controlled to select for its unshifted input S2. But when an even word is sensed, multiplexers 130 are controlled to select for either their shifted or unshifted input depending upon their bit position with regard to the defective column. For example, suppose that the defect is in an ith even column, where i is an integer designating the bit position of the column. Multiplexers 130 prior to this bit position perform no shift. But multiplexers 130 corresponding to the ith bit position and onward are controlled to select for their shifted input. Redundant column 140 would then function as the last (thirty-second in this embodiment) even column. Such SA shifting through multiplexers 125 and 230 demands rather complicated control logic. In contrast, I/O shifting control logic is relatively simple.
There is thus a need in the art for a redundancy scheme that achieves the die savings of sense-amplifier shifting and the control logic simplicity of I/O shifting.